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features applications description tlv5636 slas223c ? june 1999 ? revised april 2004 2.7-v to 5.5-v, low power, 12-bit, digital-to-analog converter with internal reference and power down digital servo control loops 12-bit voltage output dac digital offset and gain adjustment programmable internal reference industrial process control programmable settling time: machine and motion control devices ? 1 s in fast mode mass storage devices ? 3.5 s in slow mode compatible with tms320 and spi? serial ports differential nonlinearity . . . <0.5 lsb typ monotonic over temperature the tlv5636 is a 12-bit voltage output dac with a flexible 4-wire serial interface. the serial interface allows glueless interface to tms320 and spi?, qspi?, and microwire? serial ports. it is programmed with a 16-bit serial string containing 4 control and 12 data bits. the resistor string output voltage is buffered by a x2 gain rail-to-rail output buffer. the programmable settling time of the dac allows the designer to optimize speed vs power dissipation. with its on-chip programmable precision voltage reference, the tlv5636 simplifies overall system design. because of its ability to source up to 1 ma, the reference can also be used as a system reference. implemented with a cmos process, the device is designed for single supply operation from 2.7 v to 5.5 v. it is available in an 8-pin soic and 8-pin msop package to reduce board space in standard commercial and industrial temperature ranges available options package t a soic (d) msop (dgk) 0c to 70c tlv5636cd tlv5636cdgk -40c to 85c tlv5636id tlv5636idgk please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. spi, qspi are trademarks of motorola, inc.. microwire is a trademark of national semiconductor corporation. production data information is current as of publication date. copyright ? 1999?2004, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters. d?8 dgk?8 www .ti.com 12 3 4 87 6 5 din sclk cs fs v d d outref agnd d or dgk p ackage (t op view)
tlv5636 slas223c ? june 1999 ? revised april 2004 these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. functional block diagram terminal functions terminal i/o/p description name no. agnd 5 p ground cs 3 i chip select. digital input active low, used to enable/disable inputs din 1 i digital serial data input fs 4 i frame sync input out 7 o dac a analog voltage output ref 6 i/o analog reference voltage input/output sclk 2 i digital serial clock input v dd 8 p positive power supply 2 www .ti.com serial interface and control 12-bit dac latch cs din out power-on reset x2 12 2-bit control latch 2 power and speed control 2 v oltage bandgap pga with output enable 12 ref fs sclk
absolute maximum ratings recommended operating conditions electrical characteristics tlv5636 slas223c ? june 1999 ? revised april 2004 over operating free-air temperature range (unless otherwise noted) (1) unit supply voltage (v dd to agnd) 7 v reference input voltage - 0.3 v to v dd + 0.3 v digital input voltage range - 0.3 v to v dd + 0.3 v tlv5636c 0c to 70c operating free-air temperature range, t a tlv5636i -40c to 85c storage temperature range, t stg -65c to 150c lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260c (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. min nom max unit v dd = 5 v 4.5 5 5.5 v supply voltage, v dd v dd = 3 v 2.7 3 3.3 v power on reset, por 0.55 2 v dv dd = 2.7 v 2 high-level digital input voltage, v ih v dv dd = 5.5 v 2.4 dv dd = 2.7 v 0.6 low-level digital input voltage, v il v dv dd = 5.5 v 1 v dd = 5 v (1) agnd 2.048 v dd - 1.5 v reference voltage, v ref to ref terminal v dd = 3 v (1) agnd 1.024 v dd - 1.5 v load resistance, r l 2 k w load capacitance, c l 100 pf clock frequency, f clk 20 mhz tlv5636c 0 70 operating free-air temperature, t a c tlv5636i -40 85 (1) due to the x2 output buffer, a reference input voltage . (v dd - 0.4 v)/2 causes clipping of the transfer function. the output buffer of the internal reference must be disabled, if an external reference is used. over recommended operating free-air temperature range, supply voltages, and reference voltages (unless otherwise noted) power supply parameter test conditions min typ max unit no load, fast 2.3 3.3 i dd power supply current all inputs = agnd or v dd , ma slow 1.5 1.9 dac latch = 0x800 power-down supply current see figure 8 0.01 10 a zero scale (1) -65 psrr power supply rejection ratio db full scale (2) -65 (1) power supply rejection ratio at zero scale is measured by varying v dd and is given by: psrr = 20 log [(e zs (v dd max) - e zs (v dd min))/v dd max] (2) power supply rejection ratio at full scale is measured by varying v dd and is given by: psrr = 20 log [(e g (v dd max) - e g (v dd min))/v dd max] 3 www .ti.com
electrical characteristics tlv5636 slas223c ? june 1999 ? revised april 2004 over recommended operating free-air temperature range, supply voltages, and reference voltages (unless otherwise noted) static dac specifications parameter test conditions min typ max unit resolution 12 bits inl integral nonlinearity see note (1) 2 4 lsb dnl differential nonlinearity see note (2) 0.5 1 lsb e zs zero-scale error (offset error at zero scale) see note (3) 20 mv e zs tc zero-scale-error temperature coefficient see note (4) 10 v/c % of fs e g gain error see note (5) 0.6 voltage e g tc gain error temperature coefficient see note (6) 10 ppm/c (1) the relative accuracy or integral nonlinearity (inl) sometimes referred to as linearity error, is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale errors. tested from code 10 to code 4095. (2) the differential nonlinearity (dnl) sometimes referred to as differential error, is the difference between the measured and ideal 1 lsb amplitude change of any two adjacent codes. monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code. tested from code 10 to code 4095. (3) zero-scale error is the deviation from zero voltage output when the digital input code is zero. (4) zero-scale-error temperature coefficient is given by: e zs tc = [e zs (tmax) - e zs (t min )]/v ref x 10 6 /(t max - t min ). (5) gain error is the deviation from the ideal output (2v ref - 1 lsb) with an output load of 10 k w excluding the effects of the zero-error. (6) gain error temperature coefficient is given by: e g tc = [e g (t max ) - e g (t min )]/v ref x 10 6 /(t max - t min ). output specifications parameter test conditions min typ max unit v o voltage output range r l = 10 k w 0 v dd - 0.4 v % of fs output load regulation accuracy v o = 4.096 v, 2.048 v, r l = 2 k w 0.25 voltage reference pin configured as output (ref) parameter test conditions min typ max unit v ref(outl) low reference voltage 1.003 1.024 1.045 v v ref(outh) high reference voltage v dd > 4.75 v 2.027 2.048 2.068 v i ref(source) output source current 1 ma i ref(sink) output sink current -1 ma load capacitance 100 pf psrr power supply rejection ratio -65 db reference input configured as input (ref) parameter test conditions min typ max unit v i input voltage 0 v dd - 1.5 v r i input resistance 10 k w c i input capacitance 5 pf fast 1.3 reference input bandwidth ref = 0.2 v pp + 1.024 v dc mhz slow 525 reference feed through ref = 1 v pp at 1 khz + 1.024 v dc (1) -80 db (1) reference feedthrough is measured at the dac output with an input code = 0x000. digital input parameter test conditions min typ max unit i ih high-level digital input current v i = v dd 1 a i il low-level digital input current v i = 0 v -1 a c i input capacitance 8 pf 4 www .ti.com
electrical characteristics timing requirements tlv5636 slas223c ? june 1999 ? revised april 2004 over recommended operating free-air temperature range, supply voltages, and reference voltages (unless otherwise noted) analog output dynamic performance parameter test conditions min typ max unit fast 1 3 r l = 10 k w , t s(fs) output settling time (full scale) c l = 100 pf, s see note (1) slow 3.5 7 fast 0.5 1.5 r l = 10 k w , t s(cc) output settling time, code to code c l = 100 pf, s see note (2) slow 1 2 fast 8 r l = 10 k w , sr slew rate c l = 100 pf, v/s see note (3) slow 1.5 din = 0 to 1, f out = 1 khz, glitch energy 5 nv-s cs = v dd snr signal-to-noise ratio 71 75 s/(n+d) signal-to-noise + distortion 59 66 f s = 480 ksps, f out = 1 khz, db r l = 10 k w , c l = 100 pf thd total harmonic distortion -67 -59 spurious free dynamic range 59 69 (1) settling time is the time for the output signal to remain within +0.5 lsb of the final measured value for a digital input code change of 0x20 to 0xfdf and 0xfdf to 0x020 respectively. assured by design; not tested. (2) settling time is the time for the output signal to remain within +0.5 lsb of the final measured value for a digital input code change of one count. assured by design; not tested. (3) slew rate determines the time it takes for a change of the dac output from 10% to 90% full-scale voltage. digital inputs min nom max unit t su(cs-fs) setup time, cs low before fs falling edge 10 ns t su(fs-ck) setup time, fs low before first negative sclk edge 8 ns setup time, 16 th negative edge after fs low on which bit d0 is sampled before t su(c16-fs) 10 ns rising edge of fs. setup time, 16 th positive sclk edge (first positive after d0 is sampled) before cs t su(c16-cs) rising edge. if fs is used instead of 16 th positive edge to update dac, then setup 10 ns time between fs rising edge and cs rising edge. t wh sclk pulse duration high 25 ns t wl sclk pulse duration low 25 ns t su(d) setup time, data ready before sclk falling edge 8 ns t h(d) hold time, data held valid after sclk falling edge 5 ns t wh(fs) fs duration high 25 ns 5 www .ti.com
parameter measurement information tlv5636 slas223c ? june 1999 ? revised april 2004 figure 1. timing diagram 6 www .ti.com t w l sclk cs din fs d15 d14 d13 d12 d1 d0 x x 1 x 2 3 4 5 15 16 x t w h t s u ( d ) t h ( d ) t s u ( c s - f s ) t w h ( f s ) t s u ( f s - c k ) t s u ( c 1 6 - f s ) t s u ( c 1 6 - c s )
typical characteristics tlv5636 slas223c ? june 1999 ? revised april 2004 output voltage output voltage vs vs load current load current figure 2. figure 3. output voltage output voltage vs vs load current load current figure 4. figure 5. 7 v d d = 5 v , ref = int. 2 v , input code = 4095 4.1324.131 4.13 4.129 0 0.5 1 1.5 2 2.5 3 output v oltage ? v 4.133 4.134 source current ? ma 4.135 3.5 4 slow fast v d d = 3 v , ref = int. 1 v , input code = 0 slow fast 1.5 1 0.5 0 0 0.5 1 1.5 2 2.5 3 output v oltage ? v 2 2.5 sink current ? ma 3 3.5 4 v d d = 5 v , ref = int. 2 v , input code = 0 slow fast 3.5 21 0 0 0.5 1 1.5 2 2.5 3 output v oltage ? v 4 4.5 sink current ? ma 5 3.5 4 3 2.51.5 0.5 www .ti.com 2.06852.0675 2.0672.066 0 0.5 1 1.5 2 2.5 3 output v oltage ? v 2.07 2.0705 source current ? ma 2.071 3.5 4 2.06952.0698 2.068 2.0665 slow fast v d d = 3 v , ref = int. 1 v , input code = 4095
tlv5636 slas223c ? june 1999 ? revised april 2004 typical characteristics (continued) supply current supply current vs vs temperature temperature figure 6. figure 7. power down supply current total harmonic distortion and noise vs vs time frequency figure 8. figure 9. 8 1.5 1 0.5 ?40 ?30 ?20 ?10 0 20 30 supply current ? ma 2 2.5 3 40 50 70 90 10 60 80 fast mode slow mode t ? t emperature ? c v d d = 5 v , ref = 2 v , input code = 4095 1.5 1 0.5 ?40 ?30 ?20 ?10 0 10 20 2 2.5 3 30 40 50 90 60 70 80 supply current ? ma fast mode slow mode t ? t emperature ? c v d d = 3 v , ref = 1 v , input code = 4095 1.40.8 0.4 0 0 10 20 30 40 ? power down supply current ? ma 1.6 1.8 2 50 60 70 80 1.2 1 0.60.2 t ? t ime ? m s i dd ?40?50 ?80 ?100 100 1000 thd+n ? t otal harmonic distortion and noise ? db ?20 ?10 f ? frequency ? hz 0 10000 100000 ?30?60 ?70 ?90 fast mode slow mode v d d = 5 v v r e f = 1 v dc + 1 v p/p sine w ave output full scale www .ti.com
tlv5636 slas223c ? june 1999 ? revised april 2004 typical characteristics (continued) total harmonic distortion vs frequency figure 10. differential nonlinearity vs digital input code figure 11. 9 ?40?50 ?80 ?100 100 1000 thd ? t otal harmonic distortion ? db ?20 ?10 f ? frequency ? hz 0 10000 100000 ?30?60 ?70 ?90 fast mode slow mode v d d = 5 v v r e f = 1 v dc + 1 v p/p sine w ave output full scale dnl ? differential nonlinearity ? lsb digital input code 1 0.5 0 ?0.5 ?1 0 1024 2048 3072 4096 www .ti.com
tlv5636 slas223c ? june 1999 ? revised april 2004 typical characteristics (continued) integral nonlinearity vs digital input code figure 12. 10 ?4 ?3 ?2 ?1 0 1 2 3 4 0 4096 inl ? integral nonlinearity ? lsb digital input code 1024 2048 3072 www .ti.com
application information general function serial interface tlv5636 slas223c ? june 1999 ? revised april 2004 the tlv5636 is a 12-bit, single supply dac, based on a resistor string architecture. it consists of a serial interface, a speed and power-down control logic, a programmable internal reference, a resistor string, and a rail-to-rail output buffer. the output voltage (full scale determined by external reference) for each channel is given by: where ref is the reference voltage and code is the digital input value within the range of 0 10 to 2 n-1 , where n = 12 (bits). the 16-bit data word, consisting of control bits and the new dac value, is illustrated in the data format section. a power-on reset initially resets the internal latches to a defined state (all bits zero). the device has to be enabled with cs set to low. a falling edge of fs starts shifting the data bit-per-bit (starting with the msb) to the internal register on high-low transitions of sclk. after 16 bits have been transferred or fs rises, the content of the shift register is moved to the dac latch, which updates the voltage output to the new level. the serial interface of the tlv5636 can be used in two basic modes: four wire (with chip select) three wire (without chip select) using chip select (four-wire mode), it is possible to have more than one device connected to the serial port of the data source (dsp or microcontroller). figure 13 shows an example with two tlv5636s connected directly to a tms320 dsp. figure 13. tms320 interface if there is no need to have more than one device on the serial bus, then cs can be tied low. figure 14 shows an example of how to connect the tlv5636 to tms320, spi? or microwire? using only three pins. 11 2 r e f c o d e 2 n [ v ] tms320 dsp xf0 clkx dx fsx xf1 tl v5636 cs fs din sclk tl v5636 cs fs din sclk www .ti.com
serial clock and update rate (1) (2) data format tlv5636 slas223c ? june 1999 ? revised april 2004 application information (continued) figure 14. three wire interface notes on spi and microwire: before the controller starts the data transfer, the software has to generate a falling edge on the i/o pin connected to fs. if the word width is 8 bits (spi and microwire), two write operations must be performed to program the tlv5636. after the write operation(s), the dac output is updated automatically on the next positive clock edge following the sixteenth falling clock edge. the maximum serial clock frequency is given by: the maximum update rate is: note that the maximum update rate is just a theoretical value for the serial interface, as the settling time of the tlv5636 has to be considered, too. the 16-bit data word for the tlv5636 consists of two parts: program bits (d15..d12) new data (d11..d0) d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 r1 spd pwr r0 12 data bits spd : speed control bit 1 = fast mode 0 = slow mode pwr : power control bit 1 = power down 0 = normal operation the following table lists the possible combination of the register select bits: register select bits r1 r0 register 0 0 write data to dac 0 1 reserved 1 0 reserved 1 1 write data to control register 12 tms320 dsp fsx clkx dx tl v5636 sclk din fs spi i/o sck mosi tl v5636 sclk din fs microwire i/o sk so tl v5636 sclk din fs cs cs cs f s c l k m a x 1 t w h m i n t w l m i n 2 0 m h z f u p d a t e m a x 1 1 6 t w h m i n t w l m i n 1 . 2 5 m h z www .ti.com
example: tlv5636 slas223c ? june 1999 ? revised april 2004 the meaning of the 12 data bits depends on the selected register. for the dac register, the 12 data bits determine the new dac output value: data bits: dac d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 new dac value if the control register is selected, then d1, d0 of the 12 data bits are used to program the reference voltage: data bits: control d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x (1) x x x x x x x x x ref1 ref0 (1) x = don't care ref1 and ref0 determine the reference source. if internal reference is selected, ref1 and ref0 determine the reference voltage. reference bits ref1 ref0 reference 0 0 external 0 1 1.024 v 1 0 2.048 v 1 1 external caution: if external reference voltage is applied to the ref pin, external reference must be selected. set dac output, select fast mode, select internal reference at 2.048 v: set reference voltage to 2.048 v (control register): d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 1 0 write new dac value and update dac output: d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 1 0 0 new dac output value the dac output is updated on the rising clock edge after d0 is sampled. to output data consecutively using the same dac configuration, it is not necessary to program the control register again. 13 www .ti.com
linearity, offset, and gain error using single end supplies power-supply bypassing and ground management tlv5636 slas223c ? june 1999 ? revised april 2004 when an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. with a positive offset, the output voltage changes on the first code change. with a negative offset, the output voltage may not change with the first code, depending on the magnitude of the offset voltage. the output amplifier attempts to drive the output to a negative voltage. however, because the most negative supply rail is ground, the output cannot drive below ground and clamps the output at 0 v. the output voltage then remains at zero until the input code value produces a sufficient positive output voltage to overcome the negative offset voltage, resulting in the transfer function shown in figure 15 . figure 15. effect of negative offset (single supply) this offset error, not the linearity error, produces this breakpoint. the transfer function would have followed the dotted line if the output buffer could drive below the ground rail. for a dac, linearity is measured between zero-input code (all inputs 0) and full-scale code (all inputs 1) after offset and full scale are adjusted out or accounted for in some way. however, single supply operation does not allow for adjustment when the offset is negative due to the breakpoint in the transfer function. so the linearity is measured between full-scale code and the lowest code that produces a positive output voltage. printed-circuit boards that use separate analog and digital ground planes offer the best system performance. wire-wrap boards do not perform well and should not be used. the two ground planes should be connected together at the low-impedance power-supply source. the best ground connection may be achieved by connecting the dac agnd terminal to the system analog ground plane, making sure that analog ground currents are well managed and there are negligible voltage drops across the ground plane. a 0.1-f ceramic-capacitor bypass should be connected between v dd and agnd and mounted with short leads as close as possible to the device. use of ferrite beads may further isolate the system analog supply from the digital power supply. figure 16 shows the ground plane layout and bypassing technique. figure 16. power-supply bypassing 14 dac code output v oltage 0 v negative offset 0.1 m f analog ground plane 12 3 4 87 6 5 www .ti.com
definitions of specifications and terminology integral nonlinearity (inl) differential nonlinearity (dnl) zero-scale error (e zs ) gain error (e g ) total harmonic distortion (thd) signal-to-noise ratio + distortion (s/n+d) spurious free dynamic range (sfdr) tlv5636 slas223c ? june 1999 ? revised april 2004 the relative accuracy or integral nonlinearity (inl), sometimes referred to as linearity error, is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale errors. the differential nonlinearity (dnl), sometimes referred to as differential error, is the difference between the measured and ideal 1 lsb amplitude change of any two adjacent codes. monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code. zero-scale error is defined as the deviation of the output from 0 v at a digital input value of 0. gain error is the error in slope of the dac transfer function. thd is the ratio of the rms value of the first six harmonic components to the value of the fundamental signal. the value for thd is expressed in decibels. s/n+d is the ratio of the rms value of the output signal to the rms sum of all other spectral components below the nyquist frequency, including harmonics but excluding dc. the value for s/n+d is expressed in decibels. spurious free dynamic range is the difference between the rms value of the output signal and the rms value of the largest spurious signal within a specified bandwidth. the value for sfdr is expressed in decibels. 15 www .ti.com
package option addendum www.ti.com 10-jun-2014 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples tlv5636cd active soic d 8 75 green (rohs & no sb/br) cu nipdau level-1-260c-unlim 0 to 70 5636c tlv5636cdg4 active soic d 8 75 green (rohs & no sb/br) cu nipdau level-1-260c-unlim 0 to 70 5636c tlv5636cdgk active vssop dgk 8 80 green (rohs & no sb/br) cu nipdauag level-1-260c-unlim 0 to 70 ajf tlv5636cdgkg4 active vssop dgk 8 80 green (rohs & no sb/br) cu nipdauag level-1-260c-unlim 0 to 70 ajf tlv5636cdgkr active vssop dgk 8 2500 green (rohs & no sb/br) cu nipdauag level-1-260c-unlim 0 to 70 ajf tlv5636cdr active soic d 8 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim 0 to 70 5636c tlv5636id active soic d 8 75 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 5636i tlv5636idg4 active soic d 8 75 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 5636i tlv5636idgk active vssop dgk 8 80 green (rohs & no sb/br) cu nipdauag level-1-260c-unlim -40 to 85 ajg tlv5636idgkg4 active vssop dgk 8 80 green (rohs & no sb/br) cu nipdauag level-1-260c-unlim -40 to 85 ajg tlv5636idgkr active vssop dgk 8 2500 green (rohs & no sb/br) cu nipdauag level-1-260c-unlim -40 to 85 ajg tlv5636idr active soic d 8 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 5636i tlv5636idrg4 active soic d 8 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 5636i (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device.
package option addendum www.ti.com 10-jun-2014 addendum-page 2 (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant tlv5636cdgkr vssop dgk 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 q1 tlv5636cdr soic d 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 q1 tlv5636idgkr vssop dgk 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 q1 tlv5636idr soic d 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 q1 package materials information www.ti.com 16-aug-2012 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) tlv5636cdgkr vssop dgk 8 2500 367.0 367.0 35.0 tlv5636cdr soic d 8 2500 367.0 367.0 35.0 tlv5636idgkr vssop dgk 8 2500 367.0 367.0 35.0 tlv5636idr soic d 8 2500 367.0 367.0 35.0 package materials information www.ti.com 16-aug-2012 pack materials-page 2

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